Demand for electronic devices that include non-volatile memory, such as ferroelectric random access memory (FeRAM), has greatly increased. FeRAMS utilize a ferroelectric material, such as strontium bismuth tantalate (SBT) or lead zirconate titanate (PZT), as a capacitor dielectric situated between a lower electrode and an upper electrode. Both read and write operations can be performed on a FeRAM. FeRAMs also often include a titanium nitride (TiN) barrier layer that servers to inhibit diffusion of atoms from the SBT or PZT ferroelectric layers to the underlying contact or interconnect structure.
FeRAMS, however, can suffer from bit failure. A bit typically consists of a FeRAM capacitor electrically connected, typically by a contact plug, to a transistor. These “bits” are connected to a bit line. During testing, the charge on the FeRAM capacitor is transferred to the bit line. The transferred charge induces a voltage on the bit line, which is then detected by a comparator. If the voltage falls within the range assigned to a “1”, then the comparator outputs a logical “1”. Conversely, if the voltage falls within the range assigned to a “0”, then the comparator outputs a logical “0”. If the bit line voltage of a defective bit deviates and falls outside of the assigned range, the comparator may output an incorrect value. When this condition exists, a bit failure occurs. Such bit failures are undesirable because they can affect the overall yield and reliability of the device.